Question 1

Introduce yourself and your journey into semiconductors. What attracted you to chip design/manufacturing, especially given Vietnam's National Semiconductor Strategy (Decision 1018)?

Accepted Answer

Education (Microelectronics, VLSI) -> IC design/fabrication experience -> Motivation tied to VN semiconductor trend -> 3-5 year goals. Highlight specific chip projects, technology nodes, and your exact role. Show awareness of national strategy - 50,000 engineers by 2030 target.

Question 2

Describe the complete IC design flow from specification to tape-out. What risks must be mitigated at each stage for first-pass success?

Accepted Answer

Spec -> Architecture -> RTL -> Verification -> Synthesis -> DFT -> PnR -> Physical Verification -> Signoff (STA, LVS, DRC) -> GDSII -> Tape-out. The interviewer wants end-to-end understanding. Share real examples of timing or DRC issues. Distinguish front-end vs back-end.

Question 3

Explain low-power design techniques for IoT. What PPA trade-offs have you encountered in real projects?

Accepted Answer

Dynamic vs Static power -> RTL: clock gating, operand isolation -> Architecture: Multi-Vdd, DVFS, power gating -> Physical: gate sizing, Vt swapping -> Specific PPA trade-offs. Clock gating reduces 30-40% dynamic power. Most important is trade-offs. Provide specific numbers from real projects.

Question 4

Describe key steps in CMOS wafer fabrication. Given Viettel's 32nm fab, what technical challenges must be addressed?

Accepted Answer

Wafer prep -> FEOL (Oxidation, Photolithography, Etching, Ion implant) -> Gate formation -> BEOL (metallization, CMP) -> 32nm challenges. Present systematically following process order. For 32nm challenges, mention immersion lithography, high-k metal gate, strain engineering. Viettel HPT broke ground on its 32nm fab at Hoa Lac Hi-Tech Park (Jan 16, 2026, 27 hectares), targeting trial production 2027-2028. (Data as of Aug 2026. Verify latest sources)

Question 5

Compare chip packaging methods (wire bonding, flip-chip, fan-out WLP) and testing processes. Connect to FPT's ATP plant in Bac Ninh.

Accepted Answer

Wire bonding -> Flip-chip -> Fan-out WLP -> 2.5D/3D -> Testing flow: wafer probe -> die sort -> package -> final test -> burn-in. Advanced packaging is increasingly important. FPT Semiconductor established its ATP plant at Yen Phong II-C, Bac Ninh (Jan 2026): Phase 1 (2026-2027) has 1,600m2 with 6 ATE lines. Phase 2 (2028-2030) expands to 6,000m2, 24 lines, adding CSP/WLP packaging. Note: this is ATP (Assembly, Testing & Packaging), NOT a fab. (Data as of Aug 2026. Verify latest sources)

Question 6

Silicon from fab doesn't function per spec. Describe your debug methodology from failure analysis to root cause. Have you encountered this?

Accepted Answer

Triage -> Reproduce -> Isolate (ATE, scan, JTAG) -> Analyze (FIB, SEM, EMMI) -> Root cause (design vs process vs test) -> Corrective action. Show systematic thinking - don't jump to conclusions. Distinguish design bugs, process defects, test gaps. Share specific examples.

Question 7

Yield is critical. Explain yield improvement methods (DFM, SPC). How would you handle a sudden 15% yield drop?

Accepted Answer

Yield model -> DFM -> DFT -> SPC -> Yield drop handling: Pareto analysis, split lot experiment, equipment correlation. Categorize yield loss (random vs systematic). For 15% drop: check wafer maps, correlate equipment logs, review recipe changes, split lot tests.

Question 8

Describe your Cadence Virtuoso workflow for analog/mixed-signal design. How do you set up testbenches, run simulations, and ensure silicon correlation?

Accepted Answer

Schematic -> Testbench -> Spectre/ADE simulations -> PVT corners -> Monte Carlo -> Post-layout simulation -> Silicon correlation. Specify ADE Explorer or ADE XL. Explain why post-layout simulation matters (parasitic RC). Share silicon correlation experience.

Question 9

Compare Synopsys Design Compiler and ICC2 in digital design flow. How do you write SDC constraints and fix timing violations?

Accepted Answer

DC: synthesis -> ICC2: floorplan, placement, CTS, routing -> SDC constraints -> Timing closure strategy -> ECO. Fix setup violations first (buffer, resize), then hold violations (delay buffer). Emphasize Tcl scripting for automation.

Question 10

Tell me about a tape-out project. Your role, team size, technology node, and biggest challenges from RTL freeze to GDSII?

Accepted Answer

Context (chip type, application) -> Role (front-end or back-end) -> Tech node and foundry -> Team -> Challenges -> Outcome (first-pass? respin?). Use STAR. Specify tech node, foundry, EDA tools. If respin needed, share root cause. Key numbers: die size, gate count, frequency.

Question 11

Share your most significant verification experience. Which block, UVM testbench, coverage strategy, and most critical bug caught before tape-out?

Accepted Answer

Block/IP -> UVM architecture -> Constrained random vs directed -> Coverage targets -> Critical bug story. For critical bug: what corner case, why directed tests missed it. Mention assertion-based verification (SVA) and formal verification.

Question 12

Two weeks before tape-out, team discovers critical timing violation. Manager wants to ship on time. How would you handle this?

Accepted Answer

Assess severity (how many ps? which path? corner?) -> Quick fix (ECO) -> Workaround (derating, voltage margin) -> Risk assessment -> Data-driven communication. Don't say "unconditionally delay" or "ship at all costs." If small violation on worst-case corner, may accept with margin analysis. If large, propose ECO plan.

Question 13

Design and verification teams disagree about coverage closure. Design wants early tape-out, verification says coverage is insufficient. How would you resolve?

Accepted Answer

Listen to both sides -> Data-driven coverage review -> Triage: critical vs nice-to-have -> Focused tests for critical gaps -> Post-silicon validation plan. Show leadership and mediation. Categorize gaps by risk: high-risk features must close, low-risk can be waived. Coverage waiver documentation.

Question 14

Vietnam targets 50,000 chip engineers by 2030. Why do you want to work here instead of Intel, Samsung, or Marvell in Vietnam?

Accepted Answer

Company understanding -> Personal alignment -> Honest comparison (local: ownership vs MNC: process) -> Specific contributions -> Long-term vision in VN semiconductor ecosystem. Avoid generic "want to contribute to the country." For local companies: emphasize ownership. For MNCs: access to advanced nodes.

Question 15

What is your salary expectation? Have you researched semiconductor engineer salaries in Vietnam?

Accepted Answer

Market research -> Consideration factors (base, bonus, equity, training) -> Comparison (local vs MNC vs overseas) -> Your value -> Total compensation. Vietnam Semiconductor salary (gross, Aug 2026): Fresh grad 15-35M (MNC 20-35M), Junior 22-50M, Mid 35-80M, Senior 50-120M+, Lead 80-180M+. Fastest salary growth. Ask about total comp including RSU/ESOP. (Data as of Aug 2026. Verify latest)

Question 16

Do you have any questions about the team, projects, or technology direction?

Accepted Answer

Ask 2-3 questions: (1) Next chip technology node? Tape-out timeline? (2) Team structure, design/verification ratio? (3) Advanced node training programs? Don't ask questions findable on the website. Ask questions only team members can answer: tech node, EDA flow, foundry collaboration.